Nonvolatile semiconductor memory circuit utilizing a MIS transistor as a memory cell
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United States of America Patent
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Oct 26, 2010
Grant Date -
Dec 24, 2009
app pub date -
Jun 18, 2008
filing date -
Jun 18, 2008
priority date (Note) -
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Abstract
A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor in a first operation such that a lingering change is created in transistor characteristics of the MIS transistor in response to the data stored in the latch, wherein the MIS transistor includes a highly-doped substrate layer, a lightly-doped substrate layer disposed on the highly-doped substrate layer, diffusion regions formed in the lightly-doped substrate layer, a gate electrode, sidewalls, and an insulating film.
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