Methods and apparatus for dynamic frequency scaling of phase locked loops for microprocessors
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United States of America Patent
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Oct 26, 2010
Grant Date -
Jul 24, 2008
app pub date -
Jan 19, 2007
filing date -
Jan 19, 2007
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Abstract
A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.
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