System and method for verification and generation of timing exceptions
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United States of America Patent
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Oct 19, 2010
Grant Date -
Apr 24, 2008
app pub date -
Oct 23, 2007
filing date -
Oct 23, 2006
priority date (Note) -
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Abstract
The invention relates to a method for verifying one or more exceptions in a logic circuit comprising the steps of: a first step of providing an initial representation of a logic circuit; a second step of indicating at least one exception for the logic circuit; a third step of introducing one or more potential malfunctions of the logic circuit related to the one or more exceptions into the representation of the logic circuit to produce a modified representation of the logic circuit; a fourth step of determining whether functional behavior of the modified representation of the logic circuit differs from functional behavior of the first representation of the logic circuit; and a fifth step of reporting a result relating to the difference in the functional behavior of the modified representation of the logic circuit from the functional behavior of the initial representation of the logic circuit.
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