Method and system for correcting timing errors in high data rate automated test equipment

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United States of America Patent

PATENT NO 7810005
SERIAL NO

11982075

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Abstract

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A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.

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Patent Owner(s)

Patent OwnerAddress
SILICON VALLEY BANK AS ADMINISTRATIVE AGENT3003 TASMAN DRIVE HF 150 SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gazounaud, Jean-Yann St Rambert, FR 2 1
Maassen, Howard San Jose, US 8 19

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