Metal capping of damascene structures to improve reliability using hyper selective chemical-mechanical deposition
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 14, 2010
Grant Date -
Jun 1, 2006
app pub date -
Nov 29, 2004
filing date -
Nov 29, 2004
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method for improving the reliability of integrated circuits. In one embodiment, the method includes forming a dielectric layer on a semiconductor wafer. A trench is then formed in the dielectric. Thereafter, a conductive interconnect is formed within the trench, wherein the conductive interconnect comprises copper. The conductive interconnect is then etched using an acidic solution. Lastly, a conductive layer is formed on an exposed surface of the etched conductive interconnect.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully