Method of fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel
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United States of America Patent
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Sep 14, 2010
Grant Date -
Oct 13, 2005
app pub date -
Mar 28, 2005
filing date -
Mar 29, 2004
priority date (Note) -
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Abstract
A method of forming a transistor structure on a substrate (SOI) is disclosed, wherein the substrate comprises a supporting Si layer, a buried insulating layer, and a top Si layer. The method comprises forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer comprises a high dopant level. The method further comprises forming an open area on the top Si layer demarcated by a demarcating oxide and/or resist layer region, forming high level impurity or heavily-damaged regions by ion implantation, and exposing the open area to an ion beam, wherein the ion beam comprises a combination of beam energy and dose, and wherein the demarcating layer region and the gate region act as an implantation mask.
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