Analog front end timing generator (AFE/TG) having a bit slice output mode
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United States of America Patent
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Sep 7, 2010
Grant Date -
Apr 13, 2006
app pub date -
Jan 27, 2005
filing date -
Oct 11, 2004
priority date (Note) -
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status (Latency Note)
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Abstract
A versatile analog front end and timing generator (AFE/TG) integrated circuit has output modes wherein multiple identical AFE/TGs output digitized sensor data to a single digital image processor (DIP) without intervening discrete multiplexing circuitry. In one embodiment, the AFE/TG is operable in either a bit slice mode or a time slice mode. In the bit slice mode, each of the multiple AFE/TGs sections up a word of pixel information into subsets of bits, and then communicates the subsets in parallel, one subset after another, across point-to-point connections to corresponding terminals of the DIP. The DIP captures the subsets of bits, and reassembles the subsets to recreate the word of pixel information. Each of the multiple AFE/TGs communicates words of pixel information to a different set of terminals on the DIP in this way, thereby avoiding timing complications, loading and/or expense associated with communicating the pixel information using time multiplexing techniques.
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