Recessed channel transistor and method for preparing the same
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United States of America Patent
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Aug 24, 2010
Grant Date -
Jan 21, 2010
app pub date -
Jul 16, 2008
filing date -
Jul 16, 2008
priority date (Note) -
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Abstract
A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor.
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