Methods and systems for semiconductor testing using reference dice
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United States of America Patent
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Aug 17, 2010
Grant Date -
May 7, 2009
app pub date -
Dec 30, 2008
filing date -
Jul 5, 2006
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Abstract
Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.
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