Shift-add based parallel multiplication
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United States of America Patent
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Aug 10, 2010
Grant Date -
Mar 26, 2009
app pub date -
Apr 18, 2008
filing date -
Sep 24, 2007
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Abstract
A system for performing parallel multiplication on a plurality of factors. In a binary processor, a first and a second memory have pluralities of bit-positions. The first memory holds a first value as a multiplier that will commonly serve as multiple of the factors, and the second memory holds a second value that is representative of multiple multiplicands that are other of the factors. A multiplier bit-count is determined of the significant bits in the multiplier. And a +* operation is performed with the first value and said second value a quantity of times equaling the multiplier bit-count.
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