Test systems and methods for integrated circuit devices
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United States of America Patent
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Jul 27, 2010
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N/A
app pub date -
May 7, 2004
filing date -
Mar 19, 2001
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Abstract
One embodiment of the invention is a portion of a test system that includes a timing generation circuit and a formatter that are coupled together, which are on a single CMOS (complementary metal oxide semiconductor) integrated circuit. The timing Generation circuit generates software words. The formatter receives the software words and provides a specified number of transitions per second and a specified edge placement resolution and accuracy. It is noted that the formatter includes a drive circuit and a response circuit. Specifically, the drive circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent formatted level. The response circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent strobe marker.
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