Complementary MISFET formed in a linear body
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United States of America Patent
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Jul 13, 2010
Grant Date -
Dec 6, 2007
app pub date -
Oct 27, 2004
filing date -
Oct 29, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Integrated circuits such as semiconductor memories, image sensors, PLA's, and the like have been formed on rigid, planar substrates such as silicon substrates. This has resulted in shapes without flexibility and limited applicabilities. Further, since multiple circuit elements are continuously formed on a flat surface, it has been impossible to produce a non-defective semiconductor memory unless all the circuit elements are fabricated without defects, making it difficult to improve a yield. It is thus devised to weave or braid linear devices into a fabric shape to prepare a planar semiconductor memory, or to bundle up linear devices to prepare a linear semiconductor memory. The integrated circuit comprising the linear devices is flexible and light-weighted, and is thus usable in various applications. It becomes possible to prepare an integrated circuit by once fabricating linear devices and selecting only non-defective ones therefrom, thereby enabling an improved production yield of integrated circuits.

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- 15 United States
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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
IDEAL STAR INC | SENDAI-SHI MIYAGI 989-3204 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Kasama, Yasuhiko | Miyagi, JP | 59 | 641 |
Kudo, Noboru | Miyagi, JP | 10 | 77 |
Omote, Kenji | Miyagi, JP | 73 | 1271 |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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