Automatic extension of clock gating technique to fine-grained power gating
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United States of America Patent
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Jul 6, 2010
Grant Date -
Apr 17, 2008
app pub date -
Dec 7, 2007
filing date -
Jul 29, 2005
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Abstract
A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at an RTL or a gate level, the logic circuits that can be power-gated. The method of the present invention derives a sleep signal for fine-grained power-gating that may be applicable to both time-critical and non-time-critical designs.
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