ESD/EOS protection circuit and related integrated circuit
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United States of America Patent
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Jun 22, 2010
Grant Date -
Mar 19, 2009
app pub date -
Sep 18, 2007
filing date -
Sep 18, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An ESD/EOS protection circuit includes a first protection circuit and a second protection circuit. The first protection circuit is coupled between an I/O pad and a power pad and includes a first P-type transistor. The P-type transistor includes a control node, a floating gate, a first connection node, and a second connection node, wherein the first connection node of the first P-type transistor is coupled to the power pad and the second connection node of the first P-type transistor is coupled to the I/O pad. The second protection circuit is coupled between the I/O pad and a ground pad.
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