Bus architecture and method for exchanging data
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United States of America Patent
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Jun 15, 2010
Grant Date -
Feb 1, 2007
app pub date -
Jul 13, 2006
filing date -
Jul 29, 2005
priority date (Note) -
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Abstract
A bus architecture has a central processing unit, a data line and bus users. The central processing unit and the bus users are connected to the data line via a bus interface. The data line is constructed as a ring and the central processing unit has two transceiver units which can be switched between transmit and receive modes. The central processing unit provides a clocked emission of data intended for the bus users. The bus users are successively connected to the data line, and each contains a monitoring unit, which is connected to the associated bus interface and is configured for activating a transmit activity of the bus interface only after receiving a synchronization message, and otherwise blocks this activity. In a method for exchanging data with such a bus architecture, a high fault tolerance, particularly when the data line is cut through, and error locating capability are achieved.
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