MIS-transistor-based nonvolatile memory for multilevel data storage
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United States of America Patent
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Jun 8, 2010
Grant Date -
Dec 17, 2009
app pub date -
Jun 16, 2008
filing date -
Jun 16, 2008
priority date (Note) -
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Abstract
A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch.
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