Ferroelectric memory with amplification between sub bit-line and main bit-line
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 8, 2010
Grant Date -
Nov 1, 2007
app pub date -
Apr 24, 2007
filing date -
Apr 26, 2006
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory capable of suppressing increase of the chip area thereof while increasing a read voltage is obtained. This memory comprises a memory cell array including a plurality of subarrays, a sub bit line arranged on each subarray and provided to be connectable to a main bit line, a storage portion connected between the word line and the sub bit line and a first transistor having a gate connected to the sub bit line and a first source/drain region connected to the main bit line for controlling the potential of the main bit line on the basis of the potential of the sub bit line in a read operation.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully