Interface circuit and a clock output method therefor
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United States of America Patent
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May 25, 2010
Grant Date -
Oct 18, 2007
app pub date -
Apr 18, 2007
filing date -
Sep 19, 2003
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Abstract
An interface circuit outputting a clock signal and data to a data register configured to serially read in the data synchronously with the clock signal, in response to a change of a control signal for outputting the clock signal and the data from one logic level to the other logic level, the interface circuit comprising a clock output circuit configured to: detect a logic level of the clock signal when the control signal changes from the one logic level to the other logic level; output the clock signal on an as-is basis to the data register, when detecting one logic level of the clock signal; and output the clock signal after having changed from the other logic level to the one logic level, to the data register, when detecting the other logic level of the clock signal.
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