Voltage random access memory (VRAM)
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United States of America Patent
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Apr 27, 2010
Grant Date -
Apr 2, 2009
app pub date -
Dec 10, 2008
filing date -
Jul 6, 2004
priority date (Note) -
Expired
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Abstract
An integrated circuit memory cell and voltage ladder design that adapts techniques typically applied to Static Random Access Memory (SRAM) circuits to implement a compact array of analog Voltage Random Access Memory (VRAM) locations. The memory cells in the VRAM each store a digital value that controls a corresponding switch. The switch couple a particular voltage from a set of voltages generated by the ladder, to be output when that location is enabled. Multiple analog output voltages are provided by simply providing additional rows of cells.
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