Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to N wells and P wells
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United States of America Patent
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Apr 6, 2010
Grant Date -
Apr 24, 2008
app pub date -
Dec 10, 2007
filing date -
Dec 27, 2002
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Expired
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Abstract
A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.
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