Low power sigma delta modulator with successive approximation converter
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United States of America Patent
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Apr 6, 2010
Grant Date -
Nov 1, 2007
app pub date -
Nov 20, 2006
filing date -
May 19, 2005
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Abstract
A low power analog-to-digital channel includes a decimation filter coupled to a sigma-delta modulator. Various embodiments include a decimation filter including an output and a sigma-delta modulator coupled to the output of the decimation filter, where a clock frequency applied to the decimation filter is approximately a integral multiple of a sampling frequency of the sigma delta modulator. In an embodiment, the sigma-delta modulator includes one or more successive approximation converters. In an embodiment, the sigma delta modulator includes one or more area efficient integrators.
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