Chip scale package (CSP) assembly apparatus and method
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United States of America Patent
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Mar 23, 2010
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app pub date -
Jul 10, 2006
filing date -
Jul 10, 2006
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Abstract
In one embodiment the present invention includes a method of fabricating a chip scale package (CSP). The method includes forming conductive bumps on a top side of a semiconductor wafer; mounting the top side of the semiconductor wafer on adhesive tape; sawing the semiconductor wafer a first time such that a wide sawing kerf is obtained; molding the semiconductor wafer with a molding compound; and sawing the semiconductor wafer a second time to obtain the CSPs. Such method has improved efficiency as compared to many existing methods of fabricating CSPs.
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