Secure processor and system
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United States of America Patent
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Mar 16, 2010
Grant Date -
Dec 21, 2006
app pub date -
Sep 14, 2005
filing date -
Jun 17, 2005
priority date (Note) -
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Abstract
A processor includes an execution unit configured to execute a program, a bus coupled to the execution unit, a local memory coupled to the bus, a DMA unit coupled to the bus, and an interface to couple the bus to an exterior, wherein the DMA unit is configured to perform a DMA transfer process in response to instruction from the execution unit, to load information by the DMA transfer process from the exterior through the interface, to decrypt the loaded information, and to write the decrypted information to the local memory by the DMA transfer process.
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