Attenuator with bias control circuit
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United States of America Patent
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Mar 16, 2010
Grant Date -
Jan 14, 2010
app pub date -
Jul 10, 2008
filing date -
Jul 10, 2008
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An attenuator includes one or more series attenuation branches including one or more series field effect transistors (FETs) each having a gate; one or more shunt attenuation branches including one or more shunt FETs each having a gate; and a bias control FET. The bias control FET receives at its gate a first bias control signal and in response thereto produces at one of its drain and source terminals a second bias control signal. Either the first bias control signal is coupled to the gates of one or more series FETs, and the second bias control signal is coupled to the gates of the one or more shunt FETs; or the first bias control signal is coupled to the gates of the one or more shunt FETs, and the second bias control signal is coupled to the gates of the one or more series FETs.
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