FET bias circuit
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United States of America Patent
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-
Mar 2, 2010
Grant Date -
May 7, 2009
app pub date -
Jul 5, 2005
filing date -
Jul 5, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.
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