Optimization of low density parity check (LDPC) building blocks using multi-input Gilbert cells

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United States of America Patent

PATENT NO 7669106
SERIAL NO

11405646

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Described are an iterative decoder and method for implementing an iterative decoder which can be used for error correction in data communications. In one implementation, the method includes implementing a first function including a first plurality of Gilbert cells, and implementing a second function including a second plurality of Gilbert cells, where examples of the first and second functions include an equality constraint function and a parity check function. Each of the first plurality of Gilbert cells and the second plurality of Gilbert cells includes n m-input Gilbert multipliers, in which n is an integer greater than (3) and m=(n−1).

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Patent Owner(s)

Patent OwnerAddress
MARVELL ASIA PTE LTDTAI SENG CENTRE 3 IRVING ROAD #10-01 SINGAPORE 369522

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Farjadrad, Ramin Mt. View, US 67 503

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