Low voltage output buffer and method for buffering digital output data
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United States of America Patent
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Feb 23, 2010
Grant Date -
Aug 30, 2007
app pub date -
Feb 24, 2006
filing date -
Feb 24, 2006
priority date (Note) -
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Abstract
Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer (12) having first and second inputs and an output and at least one N-type isolation transistor (13, 19) having a source coupled to one or both of the second input and the output. The first input receives the data signal, the second input receives a supply potential, and the output couples to the low voltage logic device. The isolation transistor has a drain for receiving a first potential and is configured to supply a second potential to the output buffer when the gate receives a bias potential. The second potential based on the first potential. The bias potential is greater than the supply potential.
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