Method for fabricating reverse-staggered thin film transistor

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United States of America Patent

PATENT NO 7662681
APP PUB NO 20070134856A1
SERIAL NO

11609374

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Abstract

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Disclosed herein is a method for fabricating a reverse-staggered polycrystalline silicon thin film transistor, and more specifically a method for fabricating a reverse-staggered polycrystalline silicon thin film transistor wherein a phosphosilicate-spin-on-glass (P-SOG) is used for a gate insulating film. The method comprises the steps of: forming a buffer layer on an insulating substrate; forming a gate metal pattern on the buffer layer; forming a planarized gate insulating film on the gate metal pattern; depositing an amorphous silicon layer on the gate insulating film; crystallizing the amorphous silicon layer into a polycrystalline silicon layer; forming a n+ or p+ layer on the polycrystalline silicon layer; forming a source/drain metal layer on the n+ or p+ layer; and forming a passivation layer on the source/drain metal layer.

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Patent Owner(s)

Patent OwnerAddress
KYUNGHEE UNIVERSITY INDUSTRIAL & ACADEMIC COLLABORATION FOUNDATION1 HOEGI-DONG DONGDAEMUN-GU SEOUL 130-701

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cheon, Jun-Hyuk Seoul, KR 12 92
Jang, Jin Seoul, KR 97 725

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