Multilayer wiring board and method for testing the same
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United States of America Patent
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Feb 9, 2010
Grant Date -
Aug 28, 2008
app pub date -
Feb 27, 2008
filing date -
Feb 28, 2007
priority date (Note) -
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Abstract
A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. One of the conductor layers has a grounded pattern. Each of the conductor layers has a reference pattern, which is usable as a standard in calculation of an electric capacitance. An electric capacitance is measured between the grounded pattern and the three-dimensional wiring path. On the other hand, a theoretical electrical capacitance is calculated on the basis of a reference value of electric capacitance which has been measured between the reference pattern and the grounded pattern. The measured value for the wiring path is compared to the calculated value to determine whether the three-dimensional wiring path is good or bad. As the multilayer wiring section has the reference patterns, the electric capacitance for the normal wiring path can be obtained by calculation without preparing the normal acceptable product.
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