Method and system for designing test circuit in a system on chip
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Feb 2, 2010
Grant Date -
May 29, 2008
app pub date -
Oct 3, 2007
filing date -
Nov 24, 2006
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method and system for designing a test circuit in a System on Chip (SOC) includes identifying the test design constraints of the test circuit. The SOC is partitioned logically into a first set of logic blocks and a second set of logic blocks. A first set of scan chains is inserted in the first set of logic blocks, and a second set of scan chains is inserted in the second set of logic blocks, based on the test design constraints. Bypass circuits are inserted in the paths of the second set of scan chains, which are capable of bypassing at least one logic block of the second set of logic blocks during testing of the SOC.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully