CMOS silicide metal gate integration
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United States of America Patent
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Feb 2, 2010
Grant Date -
Oct 16, 2008
app pub date -
Jun 24, 2008
filing date -
Feb 25, 2004
priority date (Note) -
Expired
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Abstract
The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
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