Non-temporal memory reference control mechanism
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 12, 2010
Grant Date -
Oct 4, 2007
app pub date -
Jun 5, 2007
filing date -
Feb 19, 2002
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into a micro instruction sequence. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies a non-temporal access for a memory reference prescribed by the extended instruction, where the non-temporal access cannot be specified by an existing instruction from an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the micro instruction sequence, and executes the non-temporal access to perform the memory reference.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully