Suppression of store checking
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 12, 2010
Grant Date -
Oct 4, 2007
app pub date -
Jun 5, 2007
filing date -
Apr 2, 2002
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruction. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies that store checking be suppressed for the extended instruction. The extended prefix tag is an otherwise architectural opcode within an existing instruction set. The fetch logic precludes store checking for pending store events associated with the extended instruction. The translation logic is coupled to the fetch logic. The translation logic translates the extended instruction into a micro instruction sequence that sequence directs the microprocessor to exclude store checking during execution of a prescribed operation.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully