Method for detecting leading edge blanking parameter of power management chip
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United States of America Patent
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Jan 12, 2010
Grant Date -
Apr 9, 2009
app pub date -
Oct 4, 2007
filing date -
Oct 4, 2007
priority date (Note) -
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Abstract
A method for detecting a leading edge blanking parameter of a power management chip includes generating a pulse signal and inputting the pulse signal to the power management chip, wherein the amplitude of the pulse signal will cause a PWM signal of the power management chip to change its duty cycle; detecting the PWM signal to generate a detecting result; when the detecting result indicates that the duty cycle of the PWM signal does not change, adjusting a pulse width of the pulse signal to generate an adjusted pulse signal, inputting the adjusted pulse signal to the power management chip and detecting the PWM signal; and when the detecting result indicates that the duty cycle of the PWM signal changes, determining the leading edge blanking parameter of the power management chip according to the pulse width of the pulse signal.
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