Integrated circuit testing method and related circuit thereof
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United States of America Patent
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Jan 5, 2010
Grant Date -
Mar 12, 2009
app pub date -
Sep 11, 2007
filing date -
Sep 11, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A chip with an integrated circuit testing function includes a selecting unit positioned before a flip-flop of a scan chain, where the scan chain connects a scan-in pad, a scan-out pad and the flip-flop. When the chip is packaged and the scan-in pad does not connect to a pin of a package, the selecting unit selects a scan-in signal from another scan chain and transmits the scan-in signal from the another scan chain to the flip-flop; and when the chip is packaged and the scan-in pad connects to a pin of the package, the selecting unit selects a scan-in signal from the scan-in pad and transmits the scan-in signal from the scan-in pad to the flip-flop.
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