Scalable process and structure of JFET for small and decreasing line widths
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United States of America Patent
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Jan 5, 2010
Grant Date -
Dec 13, 2007
app pub date -
Jun 12, 2006
filing date -
Jun 12, 2006
priority date (Note) -
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Abstract
A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on top of the substrate. A nitride layer is formed on top of the oxide layer and holes are etched for the source, drain and gate contacts. A layer of polysilicon is then deposited so as to fill the holes and the polysilicon is polished back to planarize it flush with the nitride layer. The polysilicon contacts are then implanted with the types of impurities necessary for the channel type of the desired transistor and the impurities are driven into the semiconductor substrate below to form source, drain and gate regions.
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