Flip-flop circuit assembly
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United States of America Patent
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Dec 1, 2009
Grant Date -
Jun 28, 2007
app pub date -
Feb 19, 2004
filing date -
Apr 28, 2003
priority date (Note) -
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Abstract
A flip-flop circuit arrangement having a total of four differential amplifiers (1, 2, 3, 4), which are connected to one another to produce a D flip-flop, is specified. According to the suggested principle, the two shared emitter nodes (E1, E2) of the differential amplifiers (1, 2, 3, 4) are connected via a switch pair (S1, S2) to supply potential and are activated by a differential input clock signal at a control input (CN, CP). The present flip-flop circuit is operable using especially low supply voltage (VCC) and is preferably suitable for constructing frequency dividers or shift registers.
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