Semiconductor integrated circuit and image processing system using the same
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United States of America Patent
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Nov 17, 2009
Grant Date -
Apr 20, 2006
app pub date -
Oct 18, 2005
filing date -
Oct 19, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A circuit system is provided capable of improving the throughput thereof by eliminating the operational constraint that if the operating frequency of a content addressable memory is lower than the operating frequency of a system LSI, two system clocks should be provided, or the higher frequency should be synchronized with the slower system clock. A clock control circuit (103) for down-converting an internal clock (.PHI.1) of a LSI (101) is provided, and a control signal whose frequency is made lower is used to operate a content addressable memory circuit (102).
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