Probeless DC testing of CMOS I/O circuits
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 27, 2009
Grant Date -
Sep 6, 2007
app pub date -
Mar 2, 2006
filing date -
Mar 2, 2006
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method and implementation is described by which I/O input and output circuitry of a CMOS chip are measured without the need to probe the chip. Output driver transistors are used to provide marginal voltages to test input circuits, and the output driver transistors are segmented into portions where a first portion is used to provide a representative “on” current, which is coupled to a test bus that is further connected to a current comparator circuit contained within the chip. Both leakage and “on” current of the driver transistors is measured using segmented driver transistors. The output of the current comparator circuit is connected to a test scan register or to a test output from which test results are obtained digitally. The testing techniques are also applicable for other semiconductor devices.
First Claim
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