Semiconductor integrated circuit apparatus and electronic apparatus
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United States of America Patent
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Oct 6, 2009
Grant Date -
Aug 2, 2007
app pub date -
Jan 26, 2007
filing date -
Feb 1, 2006
priority date (Note) -
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Abstract
A semiconductor integrated circuit apparatus and an electronic apparatus having a power control function configured from power control MOS transistors such that leakage current and on-resistance at the time of cut-off is sufficiently small in actual use. The semiconductor integrated circuit apparatus includes a CMOS logic circuit, a first pseudo power supply line connected to a high potential side power supply terminal of the CMOS logic circuit, a second pseudo power supply line connected to a low potential side power supply terminal of the CMOS logic circuit, and a power control NchMOS transistor connected across the second pseudo power supply line and a low potential side power supply line, with the substrate and gate of the power control NchMOS transistor being electrically connected. The gate and the substrate may also be connected via a current limiter utilizing a source follower of a depletion type NchMOS transistor.

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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
COLLABO INNOVATIONS INC | 303 TERRY FOX DRIVE SUITE 300 OTTAWA K2K 3J1 |
International Classification(s)

- [Classification Symbol]
- [Patents Count]
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Ito, Minoru | Shiga , JP | 99 | 1387 |
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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