Method of manufacturing semiconductor integrated circuit device having capacitor element
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United States of America Patent
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Oct 6, 2009
Grant Date -
Mar 13, 2008
app pub date -
Oct 29, 2007
filing date -
Jul 18, 1995
priority date (Note) -
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Abstract
In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.
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