Parallel optimization using independent cell instances
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United States of America Patent
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Sep 22, 2009
Grant Date -
Jul 24, 2008
app pub date -
Jan 24, 2007
filing date -
Jan 24, 2007
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Abstract
The present invention provides a method for parallel optimization of an integrated circuit design based on the use of sets of cell instances that are independent from each other. Multiple changes to a design are analyzed in parallel by ensuring that no two cell instances that are being changed are in the same fan-in and fan-out cones. This property allows full timing analysis to be performed on a design such that multiple alternatives are explored in parallel and accurate results are obtained. By ordering the choice of cell instances to change and by ordering the alternatives to try, a greater degree of optimization is found earlier in the process.
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