Method of manufacturing a semiconductor device having damascene structures with air gaps
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United States of America Patent
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Sep 15, 2009
Grant Date -
Oct 6, 2005
app pub date -
Mar 17, 2005
filing date -
Mar 18, 2004
priority date (Note) -
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Abstract
A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises providing a substantially planar layer having a first metal layer, depositing a via level dielectric layer, patterning the via level dielectric layer, at least partly etching the via level dielectric layer, depositing a disposable layer on the at least partly etched via level dielectric layer, patterning the disposable layer, depositing a second metal layer, planarizing second metal layer, depositing permeable dielectric layer after planarizing the second metal layer, and removing the disposable layer through the permeable dielectric layer to form air gaps.
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