Test tray and handler using the test tray
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United States of America Patent
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Sep 1, 2009
Grant Date -
Jul 24, 2008
app pub date -
Jan 22, 2008
filing date -
Jan 23, 2007
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor chip test handler includes a first chamber in which packaged chips contained in a test tray are heated to high temperature or cooled to low temperature, a second chamber in which the packaged chips contained in the test tray are tested, and a third chamber in which the packaged chips contained in the test tray are cooled or heated to room temperature. The test trays are horizontally and/or vertically moved in an upright position between the first, second, and third chambers. The chambers may be arranged in a row or in a column. The test trays include a frame and a plurality of carriers into which the packaged chips are loaded. Connecting member and or projections are detachably mounted on lateral sides of the frame. A moving apparatus for moving the test trays between the first, second, and third chambers uses the connecting members and projections to push or pull the test trays into and out of the chambers.
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