Method for wafer level chip scale packaging with passive components integrated into packaging structure
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United States of America Patent
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Sep 1, 2009
Grant Date -
Jul 12, 2007
app pub date -
May 17, 2006
filing date -
Jan 12, 2006
priority date (Note) -
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Abstract
The present invention provides a Wafer Level Chip Scale Packaging structure including a die, at least one passive component, a combining layer, an isolating layer, at least one connecting wire, an internal pad and a passivation layer. The die includes a shallow connecting pad, an internal pad and an electrical component. The passive component is formed on one side of the die. The combining layer increases the binding force between the passive component and the die. The part surface on the other side of the die is overlaid with the isolation layer. The part surface of the isolation layer and the internal pad is overlaid with the connecting wire to electrically connect to the internal pad, and the passivation layer is used for protecting the die.
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