Diagnosable structured logic array
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United States of America Patent
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Aug 18, 2009
Grant Date -
N/A
app pub date -
Jun 15, 2007
filing date -
Jun 19, 2006
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A diagnosable structured logic array and associated process is provided. A base cell structure is provided comprising a logic unit comprising a plurality of input nodes, a plurality of selection nodes, and an output node, a plurality of switches coupled to the selection nodes, where the switches comprises a plurality of input lines, a selection line and an output line, a memory cell coupled to the output node, and a test address bus and a program control bus coupled to the plurality of input lines and the selection line of the plurality of switches. A state on each of the plurality of input nodes is verifiably loaded and read from the memory cell. A trusted memory block is provided. The associated process is provided for testing and verifying a plurality of truth table inputs of the logic unit.
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