Input threshold adjustment in a synchronous data sampling circuit
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United States of America Patent
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Aug 11, 2009
Grant Date -
Jan 4, 2007
app pub date -
Jul 1, 2005
filing date -
Jul 1, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A data sampler system receives a high-speed data stream and uses a first set of data samplers for sampling the data stream at a first set of clock phase angles to produce a first set of sequential data “eye” samples. A second set of data samplers, to sampled at a second set of clock phase angles that are different from the first set of clock phase angles to produce a second set of sequential data transition samples. The first set of data samplers, the data stream is sampled at the second set of clock phase angles to produce a third set of sequential data transition samples and with the second set data samplers, the data stream is sampled at a first set of clock phase angles to produce a fourth set of sequential data “eye” samples. The system alternates between the first mode and a second mode in which the results produce a reduced input offset voltage for the sampler system.
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