Method for the production of transistor structures with LDD
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United States of America Patent
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Jul 28, 2009
Grant Date -
Jun 7, 2007
app pub date -
Oct 25, 2004
filing date -
Nov 18, 2003
priority date (Note) -
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Abstract
A method for producing a transistor structure with a lightly doped drain (LDD) includes structuring a gate electrode on a gate dielectric. The method also includes etching the semiconductor body or substrate to form sloping sidewails on regions adjacent to the gate electrode, and anisotropically back-etching the spacer layer to form spacers. The gate electrode is used as a mask to implant dopant to form a source region, a drain region, and regions of lower dopant concentration. Implanting dopant is performed at a first angle relative to the upper surface of the semiconductor body or substrate to form the source and drain regions, and at a second angle relative to the upper surface of the semiconductor body or substrate, and through the spacers, to form the regions of lower dopant concentration. The first angle is greater than the second angle.
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