Void formation for semiconductor junction capacitance reduction

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7560312
APP PUB NO 20080029829A1
SERIAL NO

11462835

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Semiconductor structures having a decreased semiconductor junction capacitance of a semiconductor junction within an active semiconductor layer may be fabricated using an ion implantation and thermal annealing method. The ion implantation and thermal annealing method provides for a plurality of voids located completely within the active semiconductor layer proximate to the semiconductor junction located within the active semiconductor layer, absent stressing of the active semiconductor layer.

First Claim

See full text

Other Claims data not available

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
BUNGE GLOBAL INNOVATION LLC50 MAIN STREET WHITE PLAINS NY 10606

International Classification(s)

loading....
  • 2006 Application Filing Year
  • H01L Class
  • 15239 Applications Filed
  • 10454 Patents Issued To-Date
  • 68.61 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances2006200720082009201020112012201320142015201620172018201920200255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Xiangdong Poughquag , US 216 2796
Yang, Haining Wappingers Falls , US 189 2497

Cited Art Landscape

Load Citation

Patent Citation Ranking

  • 0 Citation Count
  • H01L Class
  • 0 % this patent is cited more than
  • 16 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges7814908714622651381027160483613101 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +01002003004005006007008009001000110012001300140015001600

Forward Cite Landscape

Load Citation