Void formation for semiconductor junction capacitance reduction
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Jul 14, 2009
Grant Date -
Feb 7, 2008
app pub date -
Aug 7, 2006
filing date -
Aug 7, 2006
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Semiconductor structures having a decreased semiconductor junction capacitance of a semiconductor junction within an active semiconductor layer may be fabricated using an ion implantation and thermal annealing method. The ion implantation and thermal annealing method provides for a plurality of voids located completely within the active semiconductor layer proximate to the semiconductor junction located within the active semiconductor layer, absent stressing of the active semiconductor layer.
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
BUNGE GLOBAL INNOVATION LLC | 50 MAIN STREET WHITE PLAINS NY 10606 |
International Classification(s)

- 2006 Application Filing Year
- H01L Class
- 15239 Applications Filed
- 10454 Patents Issued To-Date
- 68.61 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Chen, Xiangdong | Poughquag , US | 216 | 2796 |
# of filed Patents : 216 Total Citations : 2796 | |||
Yang, Haining | Wappingers Falls , US | 189 | 2497 |
# of filed Patents : 189 Total Citations : 2497 |
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- 0 Citation Count
- H01L Class
- 0 % this patent is cited more than
- 16 Age
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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