Low-power consumption high-voltage CMOS driving circuit
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United States of America Patent
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Jul 7, 2009
Grant Date -
Sep 6, 2007
app pub date -
Oct 20, 2004
filing date -
Jul 30, 2004
priority date (Note) -
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Abstract
The low power consumption CMOS high voltage driving circuit relates to a kind of high voltage driving circuit for output driving, and there is an out buffer stage between the output end of the level switch stage and the input end of the high voltage output stage, comprising a high voltage PMOS pipe and a high voltage NMOS pipe. The source of the high voltage PMOS pipe is connected with the power supply, its gate electrode is connected with the output end of the upper level out buffer unit as the input end of the current level out buffer unit. The source of the high voltage NMOS pipe is put to earth, and its gate electrode serves as the receiving end of the 3ith sequence signal. The drain region of the high voltage PMOS pipe is connected with that of the high voltage NMOS pipe and is connected with the input end of the lower level out buffer unit as the output end of the current level out buffer unit. The input end of the first out buffer unit is connected with the output end of the level switch stage as the input end of the out buffer stage, and the output end of the final output buffer unit is connected with another input end of the high voltage output stage as the output end of the out buffer stage.
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